1 A) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a fuse circuit and a dummy structure not functioning as an electronic circuit. The dummy structure may be an active region dummy, a gate electrode dummy and the like.
2 B) Description of the Related Art
Since the integration degree of recent semiconductor integrated circuit devices is high, shallow trench isolation (STI) excellent in planarization has been adopted as isolation techniques in place of local oxidation of silicon (LOCOS). Since the gate length is becoming shorter than ever, a high patterning precision is required to form a gate electrode.
For example, a buffer silicon oxide film and a silicon nitride film are formed on a silicon substrate, and an opening is formed through the buffer silicon oxide film and silicon nitride film, the opening having a shape corresponding to an isolation region which defines active regions. By using the silicon nitride film as a mask, the silicon substrate is etched to form an element separation or isolation trench.
An insulating layer such as a silicon oxide film is deposited to bury or embed the isolation trench with the insulating layer. An unnecessary insulating film deposited on the silicon nitride film is removed by chemical mechanical polishing (CMP). With the above processes, such a silicon substrate can be obtained which has an STI type isolation region and a flat surface.
The silicon nitride film used as the mask is removed and necessary ion implantation is performed to form desired wells. Thereafter, a gate oxide film and a polysilicon film are formed on the surface of the active region. The gate oxide film and polysilicon film are patterned to form a gate electrode (and word line) through anisotropic etching using a photoresist pattern. The gate electrode having a short gate length can be formed through high precision patterning.
After ions are implanted into the regions on both sides of the gate electrode to form extension regions, an insulating film such as a silicon oxide film is deposited and anisotropic etching is performed to form side wall spacers from the insulating film. By using the gate electrode and side wall spacers as a mask, ion implantation is performed to form deep and high impurity concentration source/drain regions. Annealing is performed to activate implanted impurity ions.
If the resistances of the gate electrode and source/drain regions are to be reduced, metal capable of silicidation such as Co or Ni is deposited over the silicon substrate and a silicide layer is formed on the silicon surface by a silicide process.
Thereafter, an interlayer or interlevel insulating film is deposited burying or embedding the gate electrode. An irregular surface due to the gate electrode and the like is planarized by CMP. Contact holes for deriving leads are formed through anisotropic etching. Local interconnect grooves may be formed at the same time. A metal layer such as a lamination of Ti, TiN and W is deposited to fill or bury the contact holes and other grooves with the metal layer. An unnecessary metal layer deposited on the surface of the interlayer insulating film is removed by CMP or the like. In this manner, contact plugs deriving upward the electrodes of a semiconductor device can be formed. Thereafter, necessary upper level wirings and interlayer insulating films will be formed.
If the distribution of areas of the isolation region has a large variation in an STI process, the central area of the silicon oxide film buried in a trench having a large width is polished faster than other areas, resulting in dishing. In an active region having a small width sandwiched between trench isolation regions having a large width or in a region where active regions having a small width are dense, CMP does not stop at the silicon nitride film and the active regions may be excessively polished, resulting in erosion.
If the flatness of the substrate surface is lost because of such phenomena, a later lithography process is adversely affected. High precision photolithography requires a flat surface of an underlying layer. If the surface is irregular, an image transfer precision of photolithography lowers. In order to guarantee the surface flatness, it is desired to form such an isolation region which disposes active region dummies in addition to active regions for making semiconductor elements.
Gate electrodes on the surface of a silicon substrate have a high integration degree. The highest patterning precision is required to form such gate electrodes. If the distribution of gate electrodes to be etched from a conductive layer has a variation, etch rates change with this variation. It is desired to form gate electrode dummies in order to make the distribution of gate electrodes uniform.
Such dummy patterns are generally usually automatically designed in accordance with the data processing compatible with some rules in order to reduce a design load. Some problems may occur if dummy structures are formed in such a way.
It is becoming more difficult to maintain a high yield in manufacturing highly integrated semiconductor devices. To increase the yield, generally redundant circuits are prepared to replace defective circuits with redundant circuits to recover the function of the semiconductor device. A fuse circuit is used for the replacement with the redundant circuit.
It is necessary to properly design the fuse element so as not to erroneously break it, by taking into consideration the spot diameter of a laser beam. The fuse element requires a relatively large area depending upon the spot diameter of a laser beam.
As the scale of redundant circuit becomes large and the number of fuse elements increases correspondingly, the area of a fuse circuit occupied in a semiconductor substrate becomes large. A dummy pattern DP for planarization is required to be inserted also inside a guard ring GR, similar to an ordinary circuit.
As described above, a pattern of active region dummies and gate electrode dummies is generally automatically designed. This is also true for a dummy pattern in a fuse circuit. As a dummy pattern is disposed in the fuse circuit, a margin of a fuse breaking process may be lowered or the substrate may be damaged.
There is a proposal to form a block layer of tungsten under the fuse circuit. Each fuse is broken through laser abrasion. The block layer stops the laser abrasion with good controllability. (Refer to JP-A-HEI-11-345880)